1. Field of the Invention
The present invention relates generally to semiconductor fabrication and, more particularly, to systems and methods for fabricating nanometric-scale semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks.
2. Description of Related Art
As semiconductor devices are scaled down to nanometric sizes, it becomes increasingly difficult to improve device performance. For example, conventional device scaling reducing channel length below 100 nm does not improve device performance usually expected in larger channel length due to carrier velocity saturation. Other factors such as gate dielectric scaling present further problems. Some techniques have been developed to increase the device performance including inducing a local mechanical stress upon the channel of a device. These techniques include inducing compressive stress by shallow trench isolation (STI), embedding silicon-germanium (SiGe) in the source and/or drain regions of the device, and introducing a nitride layer at a contact etch stop layer level.